Chiplet Package Estimator

Disaggregating a chip into chiplets solves a yield and cost problem, but it creates an interconnect one: the pieces now have to talk to each other across a package instead of through on-die wires. How well they can do that — the die-to-die bandwidth — is what determines whether a chiplet design performs like a monolithic one or pays a crippling communication tax. And that bandwidth lives at the seams, the shared edges between adjacent chiplets.

The physics is a bump count. Two chiplets connect through an array of micro-bumps along their shared shoreline, and the number of links is the bump density (one over the pitch squared) times the area of that bump field. Roughly half the bumps carry data and half are power and ground, so aggregate bandwidth is the data-bump count times the per-lane rate. The standard figure of merit is bandwidth per millimeter of shoreline, and this console computes it directly — naturally reproducing the ~1 TB/s/mm that advanced UCIe achieves.

That number hinges on the bump pitch, which the substrate sets. A silicon interposer supports the finest pitch — around 45 micrometers and below — for the highest bandwidth density, which is why advanced-package UCIe lives on silicon. A cheaper organic substrate manages coarser bumps near 110 micrometers, an order of magnitude lower in density, fine for less bandwidth-hungry links. Glass is an emerging middle path. The substrate choice is therefore a bandwidth-versus-cost decision, made explicit in the comparison here.

Chiplet count is the other lever: more chiplets add shared edge and total interconnect surface (and yield better individually), but each adds an interface to route, power and test. This estimator handles the interconnect-and-package side; pair it with the Chiplet Economics console for the yield-and-cost case, the Interposer Cost console for the substrate in depth, and the Package Size console for the full envelope.