ASIC Cost Estimator Console

Deciding to build a custom ASIC is, financially, a decision to spend a large sum before you have anything to sell. Unlike buying an off-the-shelf chip — where every dollar is per-unit — custom silicon front-loads the cost into NRE, the one-time engineering investment to turn an idea into a manufacturable design. Understanding that NRE, and how it amortizes, is the whole game.

The NRE has four big pieces. The design and verification team — often dozens of engineers for a year or two — is usually the largest, easily tens of millions for a complex part. Licensed IP (CPU cores, PCIe/DDR/SerDes controllers, analog blocks) carries upfront fees and sometimes per-unit royalties. EDA tools cost millions per year per seat-bundle. And the photomask set climbs brutally with the node: about $2M at 28nm, $15M at 7nm, and north of $30M at 3nm.

Amortization is the key word. Total cost per shipped unit is the recurring manufacturing cost plus NRE divided by volume, so the all-in cost starts very high at low volume and falls toward the recurring floor as volume grows. This is the cost-versus-volume curve, and it answers the central question of custom silicon: buy-vs-build. An ASIC beats an off-the-shelf part or an FPGA only when your volume is large enough that the amortized NRE drops below the premium you'd otherwise pay.

One risk the headline number hides is the respin: if the first tape-out has a bug serious enough to require a new mask set, you pay that multi-million-dollar mask cost again. Model the base case here, then ground the recurring per-unit cost with the Wafer Cost console and the program return with the Chip Profitability console.