Series & Parallel Capacitor Builder

In 2026, a server-PSU bulk-cap designer at Delta Electronics paralleling six 470 µF polymer hybrids on a 12 V output rail needs the equivalent capacitance, Vmax and ESR/n all in one view. This builder gives that view — and the breadboard SVG means new hires see why six caps in parallel is not the same as one big cap.

The series-and-parallel reciprocal rule was first stated formally by Michael Faraday in his 1832 lectures and codified in his Experimental Researches in Electricity. Faraday had stacked Leyden jars — the original capacitors — into "cascades" (his term) to multiply voltage and observed that the resulting capacitance dropped as 1/n. He also paralleled jars to add charge storage. The SI unit of capacitance was named the farad in his honour at the 1881 International Electrical Congress in Paris.

James Clerk Maxwell's 1873 Treatise on Electricity and Magnetism generalised Faraday's rules to arbitrary electrostatic networks via the capacitance matrix. The Y-Δ transform — used in 3-terminal PF-correction networks today — comes directly from Maxwell's chapter on linear electrostatic systems. Charles Proteus Steinmetz at General Electric in 1893 added the j-omega complex-number layer that turned series/parallel reactance algebra into the everyday phasor work that backs IEEE 1459-2010.

The capacitor as a stored-energy element exploded in scope through the 20th century. Marconi's 1901 transatlantic spark-gap transmitter used a parallel bank of 4 nF Leyden-style glass plates. Edison's 1907 dynamo plants leaned on series-string electrolytic banks for field-coil bypass. Westinghouse and Tesla's 1893 Niagara AC plant used parallel PF-correction caps at 25 Hz — the practice IEEE 1036-2010 still governs. By 1957 General Electric had patented the first electrical double-layer capacitor (EDLC); Maxwell Technologies commercialised single-farad cells in 1990 and the modern 3000 F SkelCap and BCAP3000 cells now form the building blocks of 800 V EV traction-link banks.

Series-string voltage stack-up is a workhorse of HV electronics. A 600 V audio tube B+ supply uses three 450 V/100 µF electrolytics in series (Ctot 33 µF, Vmax 1350 V theoretical, derated to 1000 V working) with 1 MΩ balancing resistors across each cap per IEEE C57-1995. Modern automotive 800 V SiC traction inverters chain 30+ snubber film caps in series across the DC link, each with an active balancer per IEC 60664-1 air-clearance rules.

Parallel banks dominate where ripple current and ESR matter. The Open Compute Project 12 V Yosemite-class server PSU specifies 6 × 470 µF polymer hybrid caps in parallel on the secondary — equivalent 2820 µF with ESR/n = 1/6 of a single cap and ripple-current capability 6 ×. Murata, Nichicon and KEMET all spec their AEC-Q200 polymer parts for parallel use and provide pre-engineered "cap-stack" modules per the JEDEC JESD22 reliability standard.

What does the answer really mean? An 18-cell EDLC series string giving 0.167 F at 48 V means the pack stores E = ½ × 0.167 × 48² = 192 J at full charge — enough to ride through a 1 s grid sag at 192 W per pack. Each cell still sees only 2.7 V — below the 2.85 V damage threshold of the activated-carbon electrode. Series stack-up trades capacitance for voltage with surgical precision; parallel banks trade footprint for ripple capability. Both are present in every modern power-electronics design, and this builder makes the tradeoff visible at a glance.